Default clock configuration on the PIC32MX250F128B is done via configuration bits. Configuration bits can be genrated using the MPLAB X tool: Window -> PIC Memory Views -> Configuration bits.

Only FRC and FRCPLL clock configurations will be discussed. Refer to the device datasheet for further details.

FNOSC sets the primary default clock source some possible settings are:

#pragma config FNOSC = FRC              // Oscillator Selection Bits (Fast RC Osc without PLL)
or
#pragma config FNOSC = FRCPLL           // Oscillator Selection Bits (Fast RC Osc with PLL)

FRC will generate a clock speed of 8MHz. FRCPLL will use the PLL block to generate a different clokc speed.

When using PLL the FPLLIDIV, FPLLMUL, and FPLLODIV will determine the clock speed output of the PLL. The equation is: FCPU = ((8MHz / FPLLIDIV) * FPLLMUL) / FPLLODIV

Since the input frequency to the PLL should be around 4MHz a FPLLIDIV of 2 is appropriate. Thus to generate a 16MHz clock for example the following settings could be used:

#pragma config FPLLIDIV = DIV_2         // PLL Input Divider (2x Divider)
#pragma config FPLLMUL = MUL_16         // PLL Multiplier (16x Multiplier)
#pragma config FPLLODIV = DIV_4         // System PLL Output Clock Divider (PLL Divide by 4)