32 void (*AckReceived)(void);
33 void (*AckPayloadReceived)(uint8_t * data, uint8_t length);
34 void (*MaxRetriesHit)(void);
35 void (*ReceivedPayload)(uint8_t * data, uint8_t length);
36 void (*AckPayloadSent)(void);
44 uint64_t rx_address_p0;
45 uint64_t last_tx_address;
69 void nRF24_Init(
nrf24_t * nrf_object);
70 void nRF24_OpenRxPipe(
nrf24_t * nrf_object, uint8_t pipeNum, uint64_t address);
71 void nRF24_OpenTxPipe(
nrf24_t * nrf_object, uint64_t address);
74 void nRF24_EventHandler(
nrf24_t * nrf_object);
75 #define nRF24_ISR(nrf_object) Task_Queue( (task_fn_t)nRF24_EventHandler, nrf_object)
77 void nRF24_StartListening(
nrf24_t * nrf_object);
78 void nRF24_Standby(
nrf24_t * nrf_object);
80 void nRF24_WriteReg(
nrf24_t * nrf_object, uint8_t reg_address, uint8_t value);
81 void nRF24_WriteMultReg(
nrf24_t * nrf_object, uint8_t reg_address, uint8_t *data_ptr, uint8_t length);
83 uint8_t nRF24_ReadReg(
nrf24_t * nrf_object, uint8_t reg_address);
84 uint8_t nRF24_GetPayloadLength(
nrf24_t * nrf_object);
86 void nRF24_Write(
nrf24_t * nrf_object, uint8_t * buf, uint8_t length);
87 void nRF24_Read(
nrf24_t * nrf_object, uint8_t * buf, uint8_t length);
88 void nRF24_WriteAck(
nrf24_t * nrf_object, uint8_t * buf, uint8_t length, uint8_t pipe);
90 void nRF24_SetPowerAmplificationLevel(
nrf24_t * nrf_object, nrf24_pa_level_e level);
91 void nRF24_SetDataRate(
nrf24_t * nrf_object, nrf24_datarate_e rate);
92 void nRF24_SetCRCMode(
nrf24_t * nrf_object, nrf24_crc_mode_e mode);
93 void nRF24_SetChannel(
nrf24_t * nrf_object, uint8_t channel);
94 void nRF24_SetActive(
nrf24_t * nrf_object, uint8_t active);
95 void nRF24_SetRetries(
nrf24_t * nrf_object, uint8_t delay, uint8_t count);
96 void nRF24_FlushRx(
nrf24_t * nrf_object);
97 void nRF24_FlushTx(
nrf24_t * nrf_object);
102 #define EN_RXADDR 0x02
103 #define SETUP_AW 0x03
104 #define SETUP_RETR 0x04
106 #define RF_SETUP 0x06
108 #define OBSERVE_TX 0x08
110 #define RX_ADDR_P0 0x0A
111 #define RX_ADDR_P1 0x0B
112 #define RX_ADDR_P2 0x0C
113 #define RX_ADDR_P3 0x0D
114 #define RX_ADDR_P4 0x0E
115 #define RX_ADDR_P5 0x0F
117 #define RX_PW_P0 0x11
118 #define RX_PW_P1 0x12
119 #define RX_PW_P2 0x13
120 #define RX_PW_P3 0x14
121 #define RX_PW_P4 0x15
122 #define RX_PW_P5 0x16
123 #define FIFO_STATUS 0x17
128 #define RX_ADDR_BASE RX_ADDR_P0
130 #define AW_5B 0x03 // 5 byte address
131 #define AW_4B 0x02 // 4 byte address
132 #define AW_3B 0x01 // 3 byte address
136 #define MASK_RX_DR 0x40
137 #define MASK_TX_DS 0x20
138 #define MASK_MAX_RT 0x10
163 #define CONT_WAVE 0x80
164 #define RF_DR_LOW 0x20
165 #define PLL_LOCK 0x10
166 #define RF_DR_HIGH 0x08
167 #define RF_PA_HIGH 0x04
168 #define RF_PA_LOW 0x02
176 #define PLOS_CNT 0x10
179 #define TX_REUSE 0x40
180 #define TX_FULL_FIFO 0x20 // annoyingly this has the same mnemonic as in STATUS
181 #define TX_EMPTY 0x10
183 #define RX_EMPTY 0x01
193 #define EN_ACK_PAY 0x02
194 #define EN_DYN_ACK 0x01
197 #define REGISTER_MASK 0x1F
198 #define R_REGISTER 0x00
199 #define W_REGISTER 0x20
200 #define R_RX_PAYLOAD 0x61
201 #define W_TX_PAYLOAD 0xA0
202 #define FLUSH_TX 0xE1
203 #define FLUSH_RX 0xE2
204 #define REUSE_TX_PL 0xE3
205 #define ACTIVATE 0x50
206 #define R_RX_PL_WID 0x60
207 #define W_ACK_PAYLOAD 0xA8
208 #define W_TX_PAYLOAD_NO_ACK 0xB0
void(* csn)(uint8_t)
Set SPI Ship Select Function Pointer.
Definition: nrf24.h:31
void(* ce)(uint8_t)
Set Chip Enable Function Pointer.
Definition: nrf24.h:30
uint8_t state
state of radio
Definition: nrf24.h:37